1. Field of the Invention
This invention relates to a semiconductor integrated circuit and more particularly, to a semiconductor integrated circuit of a dynamic random access memory (DRAM) or the like having a circuit for supplying a negative voltage to a semiconductor substrate.
2. Description of the Related Art
A DRAM having a single external power source is generally provided with a circuit for supplying a negative voltage to a semiconductor substrate therein. An example of a conventional negative voltage supplying circuit is shown in FIG. 1. This circuit comprises a ring oscillator section 5 including a ring oscillator for the active time use and a ring oscillator for the stand-by time use, a ring oscillator controlling section 1 for switching these two ring oscillators of the ring oscillator section 5 in accordance with a voltage of a substrate SUB, and a negative voltage generating section 6 for generating a predetermined negative voltage in accordance with an output of the ring oscillator section 5.
The ring oscillator controlling section 1 comprises a detection circuit 2 for detecting a voltage of the semiconductor substrate SUB, a buffer circuit 3 connected to the detection circuit 2 and a hysteresis circuit 4 connected to the buffer circuit 3. The detection circuit 2 has two P-channel MOS transistors Q1 and Q2 connected in series between a power source terminal TC for receiving an external power source voltage VCC and the semiconductor substrate SUB. The transistor Q1 has the gate connected to a ground potential end G, the source connected to the terminal TC and the drain connected to a node A. The transistor Q2 has the gate connected to the ground potential end G, the source connected to the node A and the drain connected to a substrate terminal TS for receiving a voltage of the substrate SUB. The node A is supplied with an output voltage of the detection circuit 2, that is, with a voltage VA corresponding to the detected voltage of the substrate SUB.
The buffer circuit 3 comprises two CMOS inverters IV0 and IV1 connected in series. The inverter IV0 as a first stage one has the input terminal connected to the node A and the inverter IV1 as a second stage one has the output terminal connected to a node B. The node B is supplied with an output voltage of the buffer circuit 3.
The hysteresis circuit 4 comprises two CMOS inverters IV2 and IV3 connected in series, and a P-channel MOS transistor Q5. The transistor Q5 has the source connected to the power source terminal TC, the drain connected to the node B, and the gate connected to a connection point of the inverters IV2 and IV3. The hysteresis circuit 4 receives the output voltage from the buffer circuit 3 and outputs a ring oscillator controlling voltage VAC to an output terminal TAC.
The ring oscillator controlling section 1, as shown above, supplies the controlling voltage VAC corresponding to the substrate voltage VSB detected by the detection circuit 2 to the ring oscillator section 5 through the output terminal TAC.
The ring oscillator section 5 supplies a voltage VRI corresponding to the controlling voltage VAC outputted from the ring oscillator controlling section 1 to the negative voltage generating section 6. The ring oscillator section 5 includes two ring oscillators respectively for the active and stand-by times uses and serves operably to select one of these two oscillators in accordance with whether the level of the controlling voltage VAC supplied from the ring oscillator section 5 is low (L) or high (H). The active time oscillator operates mainly in the active time to supply an electric current to the negative voltage generating section 6. It operates at a short period and has a large electric current supplying capacity. On the other hand, the stand-by time oscillator operates mainly in the stand-by time to supply an electric current to the negative voltage generating circuit 6. It operates at a long period in order to reduce the consumption of an electric current in the stand-by time and has a small electric current supplying capacity.
The negative voltage generating section 6 generates negative voltage corresponding to the voltage VRI supplied from the ring oscillator section 5 to supply to the substrate SUB.
Next, the operation of the conventional negative voltage supplying circuit as shown above will be explained below.
When the stand-by time oscillator is being operated to supply the voltage VRI to the negative voltage generating section 6, if the negative substrate voltage VBS is increased for any reason, that is, if the voltage VBS is approached from a certain negative value to zero, this change is detected by the detection circuit 2 and as a result, the voltage VA at the node A is increased to approach to zero. And, if the substrate voltage VSB is increased to a certain negative value and the voltage VA is attained to a predetermined threshold voltage, the controlling voltage VAC is switched its level from the L-state to the H-state. For example, it is rapidly changed from zero (0) V to a positive power source voltage VCC (for example, 5V). Accordingly, the stand-by oscillator which is in operation hitherto is stopped to operate and the active time oscillator having a large electric current supplying capacity is started to operate instead. As a result, the substrate voltage VBS starts to be decreased. At this time, the voltage VA at the node A is maintained at the power source voltage VCC (H-level) up to the time when the voltage VA becomes a voltage slightly small than the predetermined threshold voltage due to the feedback action of the transistor Q5 of the hysteresis circuit 4, so that the substrate voltage VSB is decreased up to a predetermined negative value during that time period. Thereafter, if the voltage VA becomes lower than the predetermined threshold voltage, the controlling voltage VAC is switched from the H-state to the L-state, so that the active time oscillator is stopped to operate and the stand-by oscillator starts to operate instead. Subsequently, such an operation is repeated. Consequently, the circuit shown in FIG. 1 makes it possible to maintain the substrate voltage VSB always at a negative value.
With the conventional negative voltage supplying circuit as explained above, due to the fact that in the detection circuit 2, an electric current IS is always flowed between the power source terminal TC and substrate terminal TS through the transistors Q1 and Q2, the negative voltage generating section 6 is disadvantageously required to have an electric current supplying capacity larger than that required in case when the detection circuit 2 is not used.
Thus, an object of this invention is to provide a semiconductor integrated circuit capable of detecting a voltage of a semiconductor substrate without making an electric current supplying capacity of a negative voltage generating circuit larger than that required when a detection circuit is not provided.